1. Field of the Invention
The present invention relates to a feedback-type oscillation circuit, and particularly, to power consumption reduction.
2. Description of Related Art
In recent years, reduction in power consumption is an issue in a feedback-type oscillation circuit mounted on a semiconductor device. However, since the amplitude of an oscillation signal outputted upon the activation of an oscillation circuit is usually small, if the voltage level of a supplied power source voltage is reduced, then there is a problem that the amplitude of the oscillation signal cannot be grown in a short time.
A solution of the problem is proposed in Patent Document such as Japanese Patent No. 3136600).
FIG. 5 shows a low power consumption-type oscillation circuit described in the Patent Document.
A circuit shown in FIG. 5 includes a crystal oscillation circuit 1, a level detection circuit 2, an amplifier circuit 4, and a reference voltage generating circuit 6. The reference voltage generating circuit 6 is constituted by a low-pass filter 3, a switched capacitor circuit 5, a constant current source 7, a PMOS transistor QP, and an NMOS transistor QN. Furthermore, the switched capacitor circuit 5 is constituted by an inverter 12, a discharge switch 10, a charge switch 11, and a capacitive element C.
There are a case that a signal SP inputted to the reference voltage generating circuit 6 is a pulse signal at a constant frequency and a case that a fixed signal in a constant voltage level is inputted. At this point, in each case, the voltage level of signal outputted from the reference voltage generating circuit 6 is different. Therefore, for convenience, the reference voltage generating circuit 6 will be referred to as a “frequency-voltage conversion circuit 6” in the description. Furthermore, the low power consumption-type oscillation circuit shown in FIG. 5 includes a power source voltage terminal VD and a ground voltage terminal VS. For convenience, the symbols “VD” and “VS” denote terminal names, respectively, and at the same time, denote a power source voltage and a ground voltage.
Operations of the circuits shown in FIG. 5 will be described. An oscillation signal SO outputted from the crystal oscillation circuit 1 is inputted to the level detection circuit 2. Here, the level detection circuit 2 includes a Schmitt circuit that detects the amplitude level of the inputted oscillation signal. The signal SP outputted from the level detection circuit 2 is inputted to the frequency-voltage conversion circuit 6. Then, the frequency-voltage conversion circuit 6 outputs a reference voltage VREF. The reference voltage VREF is inputted to a non-inverting input terminal of the amplifier circuit 4. The voltage outputted from the amplifier circuit 4 is inputted to an inverting input terminal of the amplifier circuit 4 and a power source voltage terminal on the high-potential side of the crystal oscillation circuit 1. Meanwhile, the ground voltage VS is inputted to a power source voltage terminal on the low-potential side of the crystal oscillation circuit 1.
Here, an operation of the Schmitt circuit included in the level detection circuit 2 will be described. The oscillation signal SO outputted from the crystal oscillation circuit 1 is inputted to the level detection circuit 2. When the amplitude of the oscillation signal SO reaches a hysteresis width VSMT controlled by the Schmitt circuit, the level detection circuit 2 outputs the pulse signal SP.
At this point, to maintain the oscillation of the oscillation signal SO outputted from the crystal oscillation circuit 1, the hysteresis width VSMT of the Schmitt circuit needs to be adjusted. It is assumed here that a threshold voltage of the PMOS transistor QP is VTP and a threshold voltage of the NMOS transistor QN is VTN. In this case, a level detection value VSMT is usually adjusted to a voltage level of about |VTP|+VTN.
A configuration and an operation of the frequency-voltage conversion circuit 6 will be described. The pulse signal SP outputted from the level detection circuit 2 is inputted to the switched capacitor circuit 5 included in the frequency-voltage conversion circuit 6. The pulse signal is inputted to the charge switch 11 as a control signal. The pulse signal is also inputted to the inverter 12. A signal (inversion signal of the pulse signal SP) outputted from the inverter 12 is inputted to the discharge switch 10 as a control signal. Thus, the discharge switch 10 and the charge switch 11 switch ON/OFF of the connection, respectively, in accordance with the control signals in different voltage levels.
By the way, one terminal of the discharge switch 10 is connected to the ground voltage terminal VS. The other terminal of the discharge switch 10 is connected to one terminal of the capacitive element C and one end of the charge switch. The other terminal of the capacitive element C is connected to the ground voltage terminal VS.
The power source voltage VD is applied to an input terminal of the constant current source 7. As a result, a signal with a constant current value IS is outputted from an output terminal of the constant current source 7. By the way, an output terminal of the constant current source 7 is connected to a node D. Additionally, the node D is connected to the other terminal of the charge switch 11, a source of the PMOS transistor QP, and an input terminal of the low-pass filter 3. Four terminals, a drain and a gate of the PMOS transistor QP and a drain and a gate of the NMOS transistor QN, are connected to each other. A source of the NMOS transistor QN is connected to the ground voltage terminal VS. The low-pass filter 3 outputs the reference voltage VREF.
When the low-level fixed signal SP is outputted from the level detection circuit 2, the connection of the charge switch 11 included in the switched capacitor circuit 5 becomes OFF. Thus, only the output terminal of the constant current source 7, the source of the PMOS transistor QP, and the input terminal of the low-pass filter 3 are connected to the node D. Here, a potential VDO (hereinafter, referred to as a drain voltage VDO) of the node D can be illustrated with Expression (1).
                              VDO          =                      VTP            +                                                            2                  ⁢                  IS                                                  β                  ⁢                                                                          ⁢                  p                                                      +            VTN            +                                                            2                  ⁢                  IS                                                  β                  ⁢                                                                          ⁢                  n                                                                    ⁢                                  ⁢                              β            ⁢                                                  ⁢            p                    =                      μ            ⁢                                                  ⁢                          p              ·              Cox              ·                              (                                  Wp                  Lp                                )                                                    ⁢                                  ⁢                              β            ⁢                                                  ⁢            n                    =                      μ            ⁢                                                  ⁢                          n              ·              Cox              ·                              (                                  Wn                  Ln                                )                                                                        (        1        )            Here, up and in denote the mobility of hole and electron, respectively. Furthermore, (Wp/Lp) and (Wn/Ln) denote ratios of “channel width/channel length” of the transistors QP and QN, respectively. Cox denotes a gate oxide film capacitance per unit area.
To reduce power consumption, the constant current IS outputted from the constant current source 7 is adjusted to a minute value. Meanwhile, the reference voltage VREF outputted from the low-pass filter 3 denotes a voltage value VRH. The drain voltage VDO also denotes the voltage value VRH. At this point, the drain voltage VDO is adjusted to a voltage level close to the power source voltage VD. To satisfy such a condition, the values of the second term and the fourth term on the right side need to be increased in Expression (1). Thus, the ratios of “channel width/channel length” of the transistors QP and QN need to be decreased.
Next, when the pulse signal SP is outputted from the level detection circuit 2 as the amplitude of the oscillation signal SO outputted from the crystal oscillation circuit 1 increases, the connection of the charge switch 11 included in the switched capacitor circuit 5 becomes ON. Furthermore, the connection of the discharge switch 10 becomes OFF. Thus, the output terminal of the constant current source 7, the source of the PMOS transistor QP, the input terminal of the low-pass filter 3, and one terminal of the capacitive element C are connected to the node D. Assuming that the current value flowing though the capacitive element C is IC, a current IC=C·VDO·f (f denotes a frequency of the pulse signal SP, and C denotes a capacitance value of the capacitive element C) flows. Thus, since the current IC in the constant current IS shunts to the ground voltage VS, the voltage value of the drain voltage VDO decreases.
At this point, the constant current value IS and the capacitance value C are adjusted so that the voltage value VRL of the reference voltage VREF outputted from the low-pass filter 3 becomes about |VTP|+VTN. Here, the low-pass filter 3 integrates and removes the ripple components generated by the switching and outputs only direct current components as the reference voltage VREF.
The reference voltage VREF outputted from the frequency-voltage conversion circuit 6 is inputted to the non-inverting input terminal of the amplifier circuit 4. Then, the reference voltage VREF is amplified by the amplifier circuit 4 with voltage gain 1 and outputted as the power source voltage ED. The power source voltage ED is inputted to the power source voltage terminal on the high-potential side of the crystal oscillation circuit 1.
Next, a timing chart shown in FIG. 6 will be described. FIG. 6 shows a timing chart of a low power consumption-type oscillation circuit described in Patent Document.
First, in a case before a time tO, the amplitude of the oscillation signal SO outputted from the crystal oscillation circuit 1 is equal to or less than the level detection value VSMT of the level detection circuit 2. Therefore, the level detection circuit 2 outputs the low-level fixed signal SP.
At this point, the connection of the charge switch 11 becomes OFF. Therefore, the reference voltage VREF outputted from the low-pass filter 3 indicates a value close to the power source voltage VD. Thus, the value of the power source voltage ED inputted to the power source voltage terminal on the high-potential side of the crystal oscillation circuit 1 is also close to the power source voltage VD. In this way, using a voltage level close to the power source voltage VD upon the activation of the oscillation circuit can quickly start up the oscillation amplitude.
Next, at the time tO, the amplitude of the oscillation signal SO outputted from the crystal oscillation circuit 1 reaches the level detection value VSMT of the level detection circuit 2. Therefore, after the time tO, the level detection circuit 2 outputs the pulse signal SP at the same frequency as the frequency of the oscillation signal SO.
At this point, the connection of the charge switch 11 repeats ON/OFF according to the frequency of the pulse signal SR Therefore, the reference voltage VREF outputted from the frequency-voltage conversion circuit 6 decreases to the sum of the threshold voltages |VTP|+VTN. The reference voltage VREF decreased to the voltage value VRL is amplified by the amplifier circuit 4 with voltage gain 1 and outputted as the power source voltage ED. Thus, the power source voltage ED inputted to the power source voltage terminal on the high-potential side of the level detection circuit 2 also indicates the voltage value VRL (about |VTP|+VTN). In this way, when the level detection circuit 2 outputs the pulse signal SP at a constant frequency, limiting the supply of the power source voltage can reduce the power consumption.
By the way, when the reference voltage VREF is reduced to the voltage value VRL, to continue outputting the pulse signal SP from the level detection circuit 2, the level detection value VSMT needs to be set lower than the voltage value VRL.
However, in the technique described in Patent Document, ON/OFF of the switches 10 and 11 included in the switched capacitor circuit 5 are repeated according to the pulse signal SP outputted from the level detection circuit 2. Therefore, the drain voltage VDO upon charging (the charge switch 11 is ON) and the drain voltage VDO upon discharging (the charge switch 11 is OFF) are different, and the drain voltage VDO swings.
In such a case, unless the low-pass filter 3 is used, the power source voltage ED outputted from the amplifier circuit 4 also swings. In this case, if the power source voltage ED decreases below the oscillation maintenance voltage of the crystal oscillation circuit 1, then the oscillation of the oscillation signal SO outputted from the crystal oscillation circuit 1 terminates. To prevent the problem, the lower limit voltage of the power source voltage ED needs to be adjusted higher than the oscillation maintenance voltage of the crystal oscillation circuit 1. However, even if the lower limit voltage of the drain voltage VDO is simply adjusted higher, the reduction effect of the power consumption is small.
Therefore, the low-pass filter 3 is used. Using the low-pass filter 3 can make the amplitude small before outputting the drain voltage VDO. As a result, the lower limit voltage of the power source voltage ED can be adjusted higher than the oscillation maintenance voltage of the crystal oscillation circuit 1. However, there is a problem that the area increases if the low-pass filter is used. Furthermore, there is a problem that the area of the low-pass filter significantly increases when the oscillation frequency is low.